TSMC revenue growth slows in October

Taiwan Semiconductor Manufacturing Co. (TSMC) reported a 16.9% year-on-year rise in October revenue, marking its slowest growth since February 2024.

Analysts expect TSMC’s sales to rise 27.4% in the current quarter.

The company’s shares are up about 37% since the start of 2024.

Last week, global tech stocks fell amid concerns over high valuations, and Scion Asset Management disclosed bearish wagers on Nvidia.

Major US tech companies are projected to spend over US$400 billion on AI development in 2026, up 21% from 2025, according to Bloomberg estimates.

Nvidia CEO Jensen Huang said the company is growing stronger each month, after meeting with TSMC CEO C.C. Wei in Taiwan and requesting more chip supplies.

TSMC Chief Executive Officer C.C. Wei said that the production capacity remains tight as it works to meet demand, with clients including Nvidia, AMD, Qualcomm, and Apple.

🔗 Source: Bloomberg

🧠 Food for thought

Implications, context, and why it matters.

TSMC’s October blip ties to packaging bottlenecks as AI demand holds

October revenue rose 16.9% which looks soft versus recent quarters, yet CoWoS packaging capped AI GPU output as tech spending heads up 21% to $400 billion in 2026 1.
CoWoS utilization sits near 60%, since new tools are still ramping rather than demand fading 2.
Capacity stays “very tight” through 2025 1. Plans reach about 70,000 wafers a month by end-2025 then roughly 90,000 by end-2026, up from about 35,000 in 2024, with relief helped by Chiayi plus the AP8 plant starting in 2026 3 1.

HBM supply tightness gives AI infrastructure buyers an edge

Samsung says its 2026 HBM output is already booked, while Nvidia may secure about 595,000 CoWoS wafers in 2026, near 60% of global demand 4 5.
Server DRAM prices climb 18-23% in Q4 2025 as cloud providers add data centers, while HBM3E pricing slips on rivalry, setting up a profitability crossover in Q1 2026 that could redirect allocations 6.
Builders and OEMs without 2026 HBM locked in should line up DDR5 (Double Data Rate 5) or LPDDR5X (low-power DDR5X), or use mature, non-leading-edge process nodes as suppliers chase DDR5 margins 6 7. Distributors and system integrators can pitch DDR5-optimized inference, since HBM scarcity nudges buyers toward KVCache offloading to cheaper DRAM; it stores previously computed model state so it can be read quickly during inference, creating a parallel market for high-capacity DDR5 modules 8 6.