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TSMC revenue climbs 31.6% to $119.9b in 2025
TSMC reported December 2025 revenue of NT$335 billion (US$10.58 billion), down 2.5% from November but up 20.4% year-on-year.
The Taiwan-based chipmaker said its full-year 2025 revenue reached NT$3.8 trillion (US$119.93 billion), a 31.6% rise from 2024.
TSMC manufactures chips for global tech companies and is a major supplier to the semiconductor industry.
🔗 Source: TSMC
🧠 Food for thought
Implications, context, and why it matters.
TSMC 2025 revenue with a seasonal December dip and solid AI demand
- December 2025 revenue was NT$335 billion, down 2.5% from November and up 20.4% year over year. Full year sales reached NT$3.8 trillion, a 31.6% gain from 2024, and the month to month dip fits normal seasonality. AI demand stayed strong.
- High performance computing (HPC), focused on AI and data center compute, made up 57% of Q3 2025 revenue 1. Management said AI accelerator sales more than tripled in 2024 and should double in 2025 2. Sanford C. Bernstein described AI build plans tied to NVIDIA Blackwell and Rubin GPU roadmaps 3. Guidance was for 2025 growth near the mid 20s in U.S. dollars 4.
Suppliers can prepare for a 2026 to 2027 capacity surge at TSMC
- Market views put 2026 capex near US$44 to 46 billion with a chance of topping US$50 billion in 2027 to 2028 5, while some reports peg 2026 near US$50 billion 6. Industry sources see 2nm output at about 40,000 wafers a month by end 2025 and 80,000 to 90,000 by end 2026 6, with Chip‑on‑Wafer‑on‑Substrate (CoWoS) near 130,000 a month by late 2026 7.
- Tool makers in backside metallization (power delivery on the wafer back), ultra‑thin wafer handling, and through‑silicon via (TSV) gear can time bids to the 2nm ramp 6.
- Arizona work spans six to as many as twelve fabs plus three to four advanced packaging sites, with P2 targeting tool move in by late 2026 and AP1 mass production in 2028 5. OSAT firms in Taiwan and local suppliers benefit as packaging scales 6. Reports cite rising orders for CoWoS and System on Integrated Chips (SoIC, TSMC’s 3D‑stacking technology) plus build‑outs of AP7 plus AP8 with a move toward CoWoS‑L 7.




