TSMC is reportedly developing an EMIB-like packaging technology with Kinsus, a Taiwan-based chip substrate maker, as it looks for alternatives amid tight CoWoS capacity for AI chips.

TSMC mainly uses CoWoS, or Chip-on-Wafer-on-Substrate, to package high-end AI processors, including chips for customers such as Nvidia and AMD.

CEO C.C. Wei has said CoWoS capacity constraints are limiting customer growth and giving Intel an opening.

The reported design differs from CoWoS in that Intel’s EMIB, or Embedded Multi-die Interconnect Bridge, places small silicon bridges directly in the package substrate. High-speed links are needed, instead of using a full silicon interposer.

Kinsus is reportedly responsible for designing and manufacturing the substrate that carries the bridge and connects the chip components above.

EMIB-style designs can improve cost, yield, and scalability for very large multi-die AI packages.

Separate reports said Nvidia and Google have shown interest in Intel’s EMIB approach.

Nvidia is evaluating the technology, while Google reportedly plans to have Intel produce more than 3 million Tensor Processing Units before 2028.

🔗 Source: Cailianshe

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