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Taiwan’s ASE breaks ground on $3.4b AI chip testing hub

ASE Technology Holding, a Taiwan-based chip packaging and testing company, has broken ground on a new facility in Kaohsiung’s Jenwu Industrial Park.

The first phase is set to start production in April 2027 as demand for AI devices rises.

CEO Tien Wu said ASE plans to invest more than NT$108.3 billion (US$3.41 billion), in the project to expand advanced IC testing capacity. It expects the second phase to begin production in October 2027.

Wu said the Jenwu facility will span about 50,000 square meters and use AI-based manufacturing tools such as visual cloud inspection systems and fully automated unmanned material handling equipment.

🔗 Source: Focus Taiwan

🧠 Food for thought

Implications, context, and why it matters.

ASE’s US$3.4 billion buildout sits inside a global spending sprint

  • It lands in a semiconductor packaging market valued at US$70.3 billion in 2024, while advanced packaging totals US$40.3 billion of that amount 1.
  • It also lines up with ASE’s 2025 spending plans. Reports say the company will lift capital expenditure (CapEx) by US$1 billion, while institutional investors expect 2025 CapEx to top US$6 billion 2.
  • That outlay helps ASE defend an estimated 13.9% share of the semiconductor packaging market, which forecasts place at US$142.6 billion by 2030 1.

Packaging and testing now steer more chip gains

  • ASE is putting weight behind testing capacity. Reports put its advanced testing growth rate at twice the pace of its packaging business, which tracks rising demand for chip testing 2.
  • Back-end semiconductor services, the packaging and testing work done after chips are manufactured, are taking a bigger role in product advances. More than 58% of logic chip companies now cite packaging innovation as a factor in device functionality, data bandwidth, and energy efficiency 1.
  • Forecasts for 2026 put advanced packaging behind more than 40% of performance gains in next-generation processors. That supports the move to chiplet designs, which combine smaller chip components in a single package 1.

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