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South Korea to build $3.1b foundry to boost chip production
South Korea is considering building a 4.5 trillion won (US$3.1 billion) foundry to manufacture chips, with funding from both state and private investment.
The proposed 12-inch, 40-nanometre foundry aims to help fabless firms develop and test chips, according to the industry ministry.
President Lee Jae Myung presided over a meeting with leaders from Samsung Electronics, SK Hynix, and other stakeholders in Seoul to lay out these plans.
Officials will also seek to locally produce defence-related semiconductors, as the country currently imports 99% of these chips.
A special committee on semiconductors will be set up under President Lee to coordinate national chip policy.
🔗 Source: Reuters
🧠 Food for thought
Implications, context, and why it matters.
Public foundry model faces uncertain economics without clear operating structure
- The 4.5 trillion won foundry proposal has missing basics. Korea has not named an operator or a site, set capacity in wafers per month, or given a build schedule. Without these, its value for fabless chip companies (which design chips but outsource manufacturing) stays speculative.
- In Taiwan, UMC and PSMC serve over 250 fabless companies across many process generations 1. South Korea’s public-private split, plus a choice between Samsung or SK Hynix as operator, will decide if access widens or if incumbents gain most.
- Sub-10nm lines in South Korea run above 90% 2. DB HiTek 8-inch fabs exceed 85%, while SK Key Foundry sits above 80%, driven by Chinese orders 3. A 40nm fab meets mid-node demand, yet unclear state and private funding splits raise execution risk.
Fabless support infrastructure creates entry point for third-party service providers
- The Ministry of Small and Medium Enterprises (SMEs) and Startups will pick 30 fabless startups for support 4. The Ministry of Science and Information and Communications Technology (ICT) set aside 22 billion won for timely AI semiconductor commercialization support 5. Vouchers will cover design, manufacturing, and verification 5. This lifts demand for multi-project wafer shuttles, process design kits, plus 40nm intellectual property (IP) blocks such as analog circuits or memory compilers.
- EDA tool providers and IP vendors can bundle cloud design platforms with Korean-language support. Time launch plans with the Fabless-Foundry Council’s 2025 Q1 meeting 4 to match multi-project wafer (MPW) pilot run schedules. The Fabless-Foundry Council is a domestic industry-government forum for chip design-manufacturing collaboration.
- The government will upgrade AI semiconductor verification systems at the Gwangju AI Cluster (a national AI computing and data hub) by year-end 5. A demo infrastructure will scale to 120 petaflops over three years, starting with 50 petaflops in 2025 5. Packaging houses and testing service providers can offer turnkey paths for fabless firms targeting these facilities.
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