Qualcomm in talks with Samsung over 2-nm chip production

Qualcomm is in talks with Samsung Electronics to manufacture chips using a two-nanometre process, according to a report by Korea Economic Daily.

The US chipmaker’s CEO Cristiano Amon was quoted by the South Korean newspaper as saying discussions are ongoing with Samsung, among other foundry firms, for contract manufacturing, with design work reportedly completed for upcoming commercialization.

Qualcomm was not immediately available for comment, while Samsung Electronics said it does not comment on specific customers.

Samsung Electronics, based in South Korea, recently signed a US$16.5 billion supply deal with Tesla and has been pursuing new customers for its foundry business.

🔗 Source: Reuters

🧠 Food for thought

Implications, context, and why it matters.

Samsung’s 2nm yields determine if Qualcomm can diversify from TSMC

Samsung’s SF2 (its first 2nm process) yields at 50-60% for working chips per wafer. Taiwan Semiconductor Manufacturing Company (TSMC)’s N2 sits near 80% 1. That gap steers whether Qualcomm shifts volume or uses Samsung for price leverage.
Samsung plans SF2 for mobile in 2025 and for High-Performance Computing (HPC) in 2026 2. Qualcomm needs stable yields across a broader mix than internal Exynos (Samsung’s in-house smartphone processor) work.
TSMC plans 10-20% per-wafer price increases for N2 1. Samsung can undercut on cost, though Qualcomm would carry risk of supply hiccups or performance swings on a less mature process.

Samsung’s foundry expansion brings openings for EDA and IP vendors

Samsung certified Siemens’ Electronic Design Automation (EDA) tools including Calibre, Solido, and Aprisa across 14nm through SF2/SF2P (a performance-enhanced 2nm variant) 3. It partnered with Synopsys on 3D Integrated Circuit (3DIC) Compiler for I-CubeS 2.5D packaging (side-by-side chips on an advanced interposer) 4. This opens doors for EDA firms and specialty intellectual property (IP) providers of reusable chip design blocks.
Synopsys offers interface IP for Samsung’s nodes including SF2/SF2P 4. It covers 224G high speed links; Universal Chiplet Interconnect Express (UCIe); Peripheral Component Interconnect Express (PCIe) 7.0; and Low-Power Double Data Rate (LPDDR6X) memory. Samsung’s MDI (Multi-Die Integration) Alliance for 2.5D and 3D packaging 2 creates openings for Outsourced Semiconductor Assembly and Test (OSAT) providers. Chiplet architectures (systems built from multiple smaller dies connected in one package) spread in AI and High-Performance Computing (HPC) where Samsung targets 2026 production 2.