Nvidia launches first US-made Blackwell chip with TSMC

Nvidia and TSMC have produced the first Nvidia Blackwell wafer in the US at TSMC’s Phoenix facility, marking the start of volume production for the AI chip.

Nvidia CEO Jensen Huang attended the event alongside TSMC executives to commemorate the milestone.

The Blackwell wafer will be processed at TSMC Arizona, which will manufacture advanced chips for AI, telecommunications, and high-performance computing using 2-, 3-, and 4-nanometer processes as well as A16 chips.

The companies said this development strengthens the US semiconductor supply chain as demand for AI hardware rises.

Nvidia also plans to use its AI, robotics, and digital twin technology in future US manufacturing facilities.

🔗 Source: Nvidia

🧠 Food for thought

Implications, context, and why it matters.

US Blackwell production still requires overseas advanced packaging, delaying full supply chain localization

TSMC makes Blackwell wafers in Arizona 1 2 3. The chips then go to Taiwan for Chip‑on‑Wafer‑on‑Substrate packaging, CoWoS (specifically CoWoS‑L), which is a post‑fabrication step that integrates multiple dies with memory into a finished module because TSMC lacks US advanced packaging 1 2 3.
TSMC signed a Memorandum of Understanding with Amkor, an outsourced semiconductor assembly and test (OSAT) provider 2. The plan supports Integrated Fan‑Out and CoWoS in Arizona but the line is not running yet 2. Two US packaging sites are slated to start build in 2028 4 3. Their focus is System on Integrated Chips 3D stacking plus Co‑Packaged Optics, not the CoWoS‑L used by Blackwell 4 3.
These sites take at least four years to build because they need metal bumping infrastructure and a local materials supply chain 2. Metal bumping is the solder micro‑bump process 2. If US work starts in 2028, domestic packaging for these GPUs likely arrives in the early 2030s, which would cap near term resilience even with local wafer output 4 2.

Suppliers of CoWoS equipment, High Bandwidth Memory (HBM) assembly, and substrates can capture demand by targeting TSMC’s Arizona packaging buildout

TSMC and its construction partners are hiring CoWoS equipment engineers in the U.S. 3. The company often pairs three fabs with one advanced packaging plant 2. After Arizona’s third fab, Fab 21 Phase 3 (F21 P3), breaks ground in 2025, a CoWoS capable site is expected to follow 2.
Vendors covering CoWoS tools, HBM assembly, plus package substrates (the laminated bases that connect chips to circuit boards) should track the Arizona build to time partnerships and capital 2. Contractors can seek long term deals as TSMC scales System on Integrated Chips with CoWoS in the US to serve Apple, NVIDIA, AMD 4.
Orders for advanced packaging tend to lag 5. Customers place small starter buys, then much larger follow ups when demand spikes 5. Early partners should gain as US fabs come online while CoWoS output moves toward 100,000 units each month by end 2026 5.