🧠 Food for thought

Implications, context, and why it matters.

Rapidus lacks commercial readiness despite 2nm AI tool hype

• Rapidus ran 2-nanometer Gate-All-Around (GAA) transistors in July 2025 1. Mass output at its first fab has not begun 2, with volume targeted for the second half of FY2027 3.
• No public data covers yields or risk production (pilot runs before volume manufacturing) timing 3. Only IBM and Tenstorrent, an AI chip and RISC-V processor startup, sit on the list as “prospective” partners 3.
• TSMC targets 1.4-nanometer output in H2 2028 3. Rapidus begins 1.4-nanometer R&D in FY2026, about a year behind TSMC and near Samsung’s revised 2029 plan 3. Funding totals ¥100 billion this FY with ¥1 trillion slated for 2026–2027, yet the firm calls media reports on fab construction speculative, so execution risk stays high 3.

Semiconductor talent shortage creates training market opportunity in Japan

• The industry needs over 100,000 skilled workers each year through 2030, while use of AI-driven Electronic Design Automation (EDA) tools rose from zero to over half of Japan’s cutting-edge projects 45.
• AI-assisted chip design rises as Rapidus and partners like Synopsys, a leading EDA software vendor, seek engineers fluent in AI-powered EDA tools 16. GAA transistor expertise for 2-nanometer process integration is the other gap 7.
• Taiwan’s National Yunlin University offers full tuition waivers near $15,000 and monthly stipends around $320, funded by corporate donations 8. Japan’s ¥2 trillion AI plus semiconductor stimulus can fund training in AI-EDA integration, advanced packaging (techniques for stacking while tightly connecting multiple chips), and GAA process engineering 5.