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Japan gov’t to inject $640m equity funding into Rapidus chipmaker
Rapidus, a state-backed Japanese chipmaker, plans to go public around fiscal 2031.
The government will invest about ¥100 billion (US$640 million) through an equity facility.
Rapidus aims to start mass-producing 2-nanometer chips in fiscal 2027 and expects positive free cash flow by fiscal 2029.
The company will boost manufacturing at its Hokkaido factory with about ¥150 billion (US$959.1 million) in fiscal 2026 and is targeting about ¥1 trillion (US$6.4 billion) in private sector funding through fiscal 2031.
Japan’s push to strengthen its domestic semiconductor industry comes amid concerns over dependence on Taiwanese chip supply.
🔗 Source: Bloomberg
🧠 Food for thought
Implications, context, and why it matters.
Rapidus’s 2027 mass production target faces technical and execution hurdles
- Rapidus targets 2 nm mass production in fiscal 2027. Japan’s first NXE:3800E Extreme Ultraviolet (EUV) tool arrived in December 2024 1. A pilot line, a pre‑production line to validate processes, starts in April 2025 1. That leaves about two years to debug, validate yields, and scale from single‑wafer prototypes to volume.
- Plans call for up to 10 EUV tools across IIM‑1 and IIM‑2, Hokkaido modules 2. TrendForce pegs output at roughly 17,000–20,000 wafers per month with five tools 2. That trails TSMC. Samsung said High Numerical Aperture (High NA) EUV could cut cycle time by about 60% 3, yet Rapidus has an NXE:3800E, not High NA 1.
- Positive free cash flow by fiscal 2029 depends on execution and ecosystem. EDA partnerships with Synopsys, Cadence, and Siemens are recent 45. Reports of upfront intellectual property (IP) vendor payments 6 suggest the royalty‑driven ecosystem still needs support, clouding profitability.
EDA and IP vendors can capitalize on Rapidus’s design-manufacturing co-optimization gaps
- Design for Manufacturing and Co‑Optimization (DMCO) lets EDA vendors and design shops sell libraries, reference flows, and AI tools for 2 nm Gate‑All‑Around (GAA) transistors 45. Backside power delivery routes power through the wafer’s back side to reduce resistance and improve performance 7.
- Single‑wafer runs and 15–50 day turnarounds 6 force rapid Process Design Kit (PDK) iteration and Manufacturing for Design (MFD) 8. Cloud EDA and agile verification track updates, while upfront payments give smaller IP and consultancies leverage through FY2031 86.
Recent Rapidus developments
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