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Israeli chipmaker Tower Semiconductor hits $10b valuation

Tower Semiconductor, an Israeli analog chipmaker, has reached a US$10 billion valuation two years after Intel’s failed US$5 billion acquisition.

The company reported Q3 revenue of US$396 million, up 6% from the prior quarter, and net income of US$54 million, beating analyst forecasts.

Tower plans to invest US$300 million to expand AI-focused chip production in four global plants, including one in Israel, extending silicon photonics and silicon–germanium manufacturing beyond its Newport, US facility.

The company expects record Q4 2025 revenue of US$440 million, which would bring projected annual revenue to US$1.5 billion.

🔗 Source: Calcalist

🧠 Food for thought

Implications, context, and why it matters.

Tower expands photonics capacity amid AI demand; public material names no customer commitments

  • Tower is putting $300 million into silicon photonics (SiPho) and silicon-germanium (SiGe) for AI infrastructure, while public material lists no named customers or long-term deals 1.
  • SiPho is changing data center design by shifting optical links from system level to chip level, while Chinese makers TeraHop and Hisense scale with state support 23.
  • Success depends on standards. Interconnect plus protocol rules are still shifting, which could slow chiplet adoption (small specialized dies combined in one package) and photonic integration timing 4.
  • Co-packaged optics (integrating optical engines with network switches in one package) is slated for use in 2028 to 2030 3. New capacity may arrive earlier, so Tower’s outlook leans on data center demand 1.

Outsourced Semiconductor Assembly and Test (OSAT) and packaging firms should time photonics bets

  • Tower’s buildout could lift demand for photonics assembly and test 5. Fiber-to-PIC (photonic integrated circuit) assembly, active alignment, and wafer-scale vertical couplers matter.
  • Packaging firms that blend electronic and photonic ICs (integrated circuits) can prep for ramps with partnerships, using 3D stacking via TSVs (through-silicon vias) plus chip-on-wafer solutions (mounting diced chips directly onto a wafer) 5.
  • Tool makers focused on high-density RDLs (redistribution layers) with 0.5 μm/0.5 μm lines can meet 2.5D packaging requirements (side-by-side dies connected via an interposer) for AI chiplets 5.
  • Materials and thermal firms can tackle power efficiency for 200G/channel optical links (200 gigabits per second per channel) likely mainstream in 2026 to 2027 3.

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