IBM: AMD chips can run quantum error correction algorithm

IBM can run a quantum computing error correction algorithm on commercially available chips from AMD, marking progress toward more practical quantum computers.

The company showed the algorithm operating on AMD’s field-programmable gate array chips, according to a research paper to be published on October 27.

Quantum computers, which use qubits to solve complex problems, are prone to errors that affect reliability.

IBM previously announced this error correction algorithm in June, and now says it can run in real time on standard AMD hardware.

IBM is working to build a quantum computer called Starling by 2029 and said the algorithm work was completed a year ahead of schedule.

IBM shares closed up 7.9% at US$397.46, and AMD shares rose 7.6% to US$252.92 after the news.

IBM’s Jay Gambetta said the new approach is faster and less expensive than earlier methods.

🔗 Source: Reuters

🧠 Food for thought

Implications, context, and why it matters.

IBM does not name the quantum error correction (QEC) scheme, likely surface codes 1. It also omits the code distance, a parameter for how many physical errors the code can tolerate. That leaves no basis to judge support for logical qubits, which are error-corrected, encoded qubits.
Decoding often must finish within about 1 microsecond to fit coherence windows 1. The release gives no end to end latency or throughput for AMD FPGAs, so the real time claim is unproven.
IBM offers no comparison to GPU or application-specific integrated circuit (ASIC) decoders, so readers cannot weigh FPGA speed, cost, or accuracy for practical use. AlphaQubit delivers lower logical error rates than tensor network and minimum weight perfect matching decoders on Google’s Sycamore processor, a superconducting quantum chip 1.
Peer review and reproducibility remain unclear. Use of open-source intellectual property (IP) cores, which are pre-built design blocks, versus proprietary designs will guide adoption by quantum labs and startups.
If commodity AMD FPGAs handle decoding for surface codes at scale, vendors with systems integrators can package quantum control and decoder IP cores 1. Surface codes encode a logical qubit in a d×d grid of physical qubits 1.
Hardware providers could bundle low latency networking and time sync with FPGA decoders, which helps control loops protect coherence during error correction.
Independent testing firms can offer benchmarking plus certification across FPGAs, GPUs and ASICs while grading logical error rates with error suppression factors, which track how error falls as code distance rises 1.