🧠 Food for thought

Implications, context, and why it matters.

China chip surge hides HBM and packaging bottlenecks

• IC output rose 10.2% year over year to 386.6 billion units 1. It leaves open whether domestic players can both build and package AI-grade or automotive-grade chips at advanced nodes with High Bandwidth Memory (HBM) plus 2.5D/3D packaging (advanced chip-stacking with interposer techniques that place memory near compute) needed for competitive accelerators 1.
• Foundries such as Semiconductor Manufacturing International Corporation (SMIC) can fabricate AI processors, and an HBM shortfall limits real supply 2. Huawei’s Ascend 910C could reach 805,000 units a year without that bottleneck, and a cache of about 11.4 million Samsung HBM stacks bought before controls tightened will not support long-run scaling 2. Domestic HBM3E (a current-generation HBM variant) looks feasible in 2026 at the earliest if equipment access stays stable, so ambitions stay capped despite rising wafer counts 2.

RISC-V’s rise in China boosts demand for software and certification

• Software firms and tool vendors in China face a pivot to Reduced Instruction Set Computer Five (RISC-V) that creates openings across compilers, runtimes, EDA and operating systems 3. NVIDIA is porting its Compute Unified Device Architecture (CUDA) stack to RISC-V CPUs, which will need middleware and performance tuning layers 3.
• Auto plus AI chip teams adopting RISC-V will require functional safety certification (ISO 26262, an international automotive safety standard), security verification tools and specialized debugging that depart from established Arm or x86 toolchains. Western EDA suppliers such as Siemens, Cadence, and Synopsys hold 82% of China’s EDA market 4. The shift could help niche players with RISC-V-tuned design flows, verification suites or open-source tool support gain ground if export controls tighten.