ASML says first high-NA chips due in months

ASML, a Dutch chip equipment maker, said at an imec conference in Antwerp on May 19 that the first chips produced with its next-generation High-NA EUV machines should arrive within months.

The Dutch chip equipment maker said the milestone could help address concerns over the high cost of the technology.

The first products would include memory and logic chips, CEO Christophe Fouquet said.

He added that the systems are expensive and still need qualification but are intended to cut patterning costs over time.

TSMC said in April the machines, which can cost up to US$400 million each, are too expensive for now.

It plans to keep using ASML’s current EUV tools for the next several chip generations, while Intel and memory makers such as SK Hynix have signaled earlier adoption.

🔗 Source: Reuters

🧠 Food for thought

Implications, context, and why it matters.

Intel is treating early high-NA EUV as a research bet, not broad production

Intel has fully installed two High-NA EUV machines to develop its 14A process, a manufacturing process for advanced chips. The company has processed 30,000 wafers on the tools 1.
The first readout looks promising. Reliability has reached 85%, and power use is above target. Intel says that is ahead of earlier EUV systems at the same stage 1.
The cost case is narrow. IBM calculates that one High-NA exposure costs about 2.5 times as much as one low-NA exposure, ASML’s current EUV generation 1.
Savings appear when High-NA can replace flows that need three or more low-NA masks. That helps explain TSMC’s caution on cost and Intel’s focus on a small set of chip layers 1.

High-NA is creating two paths for chipmaking

TSMC is moving differently from Intel and Samsung, the South Korean electronics and chipmaker. That split leaves equipment and materials suppliers backing two costly roadmaps 2.
Chip designers also face a choice. A process tuned for High-NA can carry different design rules than one built around existing multi-patterning techniques, where several patterning steps create very small features. That raises the risk of ecosystem lock-in 1.
Memory makers face a shorter window. The move toward 3D DRAM architectures, a way of stacking DRAM memory cells vertically, may reduce the need for either High-NA or low-NA EUV in future DRAM 2.
That could leave logic foundries, companies that make advanced processor chips for customers, carrying more of the research and equipment bill. The financial pressure is higher for early users such as Intel 2.